Semiconductor device including vertically integrated groups of semiconductor packages

ABSTRACT

A semiconductor device is disclosed including at least first and second vertically stacked and interconnected groups of semiconductor packages. The first and second groups of semiconductor packages may differ from each other in the number of packages and functionality.

BACKGROUND

The strong growth in demand for portable consumer electronics is drivingthe need for high-capacity storage devices. Non-volatile semiconductormemory devices, such as flash memory storage cards, are becoming widelyused to meet the ever-growing demands on digital information storage andexchange. Their portability, versatility and rugged design, along withtheir high reliability and large capacity, have made such memory devicesideal for use in a wide variety of electronic devices, including forexample digital cameras, digital music players, video game consoles,PDAs and cellular telephones.

While many varied packaging configurations are known, flash memorystorage cards may in general be fabricated as system-in-a-package (SiP)or multichip modules (MCM), where a plurality of die are mounted andinterconnected on a small footprint substrate. The substrate may ingeneral include a rigid, dielectric base having a conductive layeretched on one or both sides. Electrical connections are formed betweenthe die and the conductive layer(s), and the conductive layer(s) providean electric lead structure for connection of the die to a host device.Once electrical connections between the die and substrate are made, theassembly is then typically encased in a molding compound which providesa protective package.

In order to most efficiently use package footprint, it is known to stacksemiconductor die on top of each other. In order to provide access tobond pads on the semiconductor die, the die are stacked, eithercompletely overlapping each other with a spacer layer in betweenadjacent die, or with an offset. In an offset configuration, a die isstacked on top of another die so that the bond pads of the lower die areleft exposed.

As semiconductor die become thinner, and in order to increase memorycapacity in semiconductor packages, the number of die stacked within asemiconductor package continues to increase. However, this can make forlong bonds wire from the upper die down to the substrate. Long wirebonds are easily damaged or electrically shorted to other wire bonds,and also have higher signal to noise ratio than shorter bond wires.Moreover, larger numbers of semiconductor die in a package can adverselyaffect yields.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart of the overall fabrication process ofsemiconductor device according to embodiments of the present technology.

FIG. 2 is a side view of a semiconductor device at a first step in thefabrication process according to an embodiment of the presenttechnology.

FIG. 3 is a top view of a semiconductor device at a second step in thefabrication process according to an embodiment of the presenttechnology.

FIG. 4 is a side view of a semiconductor device at a third step in thefabrication process according to an embodiment of the presenttechnology.

FIG. 5 is a side view of a semiconductor device at a fourth step in thefabrication process according to an embodiment of the presenttechnology.

FIG. 6 is a side view of a semiconductor device at a fifth step in thefabrication process according to an embodiment of the presenttechnology.

FIG. 7 is a simplified perspective view of a semiconductor device at thefifth step in the fabrication process according to an embodiment of thepresent technology.

FIG. 8 is a side view of a semiconductor device at a sixth step in thefabrication process according to an embodiment of the presenttechnology.

FIG. 9 is a simplified perspective view of a semiconductor device at thesixth step in the fabrication process according to an embodiment of thepresent technology.

FIG. 10 is a side cross-sectional view of a semiconductor device withina mold chase for encapsulating the semiconductor device.

FIG. 11 is a side view of a first completed semiconductor packageaccording to an embodiment of the present technology.

FIGS. 12-18 show the first semiconductor package mounted to a group ofone or more second semiconductor packages in a variety of configurationsaccording to example embodiments of the present technology.

DETAILED DESCRIPTION

The present technology will now be described with reference to thefigures, which in embodiments, relate to a semiconductor deviceincluding vertically stacked and interconnected groups of semiconductorpackages. The first and second groups of semiconductor packages maydiffer from each other in the number of packages and functionality.

It is understood that the present technology may be embodied in manydifferent forms and should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete and will fully conveythe technology to those skilled in the art. Indeed, the technology isintended to cover alternatives, modifications and equivalents of theseembodiments, which are included within the scope and spirit of thetechnology as defined by the appended claims. Furthermore, in thefollowing detailed description of the present technology, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present technology. However, it will be clear tothose of ordinary skill in the art that the present technology may bepracticed without such specific details.

The terms “top” and “bottom,” “upper” and “lower” and “vertical” and“horizontal” as may be used herein are by way of example andillustrative purposes only, and are not meant to limit the descriptionof the technology inasmuch as the referenced item can be exchanged inposition and orientation. Also, as used herein, the terms“substantially,” “approximately” and/or “about” mean that the specifieddimension or parameter may be varied within an acceptable manufacturingtolerance for a given application. In one embodiment, the acceptablemanufacturing tolerance is ±0.25%.

An embodiment of the present technology will now be explained withreference to the flowchart of FIG. 1 and the top, side and perspectiveviews of FIGS. 2 through 18. Although FIGS. 2 through 18 each show anindividual semiconductor package 100 and/or 170, or a portion thereof,it is understood that the packages 100 and 170 may be batch processedalong with a plurality of other packages on substrate panels to achieveeconomies of scale. The number of rows and columns of packages 100, 170on the substrate panels may vary.

The substrate panel for the fabrication of semiconductor package 100begins with a plurality of substrates 102 (again, one such substrate isshown in FIGS. 2 through 18). The substrate 102 may be a variety ofdifferent chip carrier mediums, including a printed circuit board (PCB),a leadframe or a tape automated bonded (TAB) tape. Where substrate 102is a PCB, the substrate may be formed of a core 103 having a topconductive layer 105 and a bottom conductive layer 107 as shown in FIG.2. The core 103 may be formed of various dielectric materials such asfor example, polyimide laminates, epoxy resins including FR4 and FR5,bismaleimide triazine (BT), and the like. The core may have a thicknessof between 40 microns (μm) to 200 μm, although the thickness of the coremay vary outside of that range in alternative embodiments. The core 103may be ceramic or organic in alternative embodiments.

The conductive layers 105, 107 surrounding the core may be formed ofcopper or copper alloys, plated copper or plated copper alloys, Alloy 42(42Fe/58Ni), copper plated steel, or other metals and materials suitablefor use on substrate panels. The conductive layers may have a thicknessof about 10 μm to 25 μm although the thickness of the layers may varyoutside of that range in alternative embodiments.

FIG. 1 is a flowchart of the fabrication process for forming asemiconductor device 180 according to embodiments of the presenttechnology. In a step 200, the substrate 102 of a first semiconductorpackage 100 may be drilled to define through-hole vias 104 in thesubstrate 102. The vias 104 are by way of example, and the substrate 102may include many more vias 104 than are shown in the figures, and theymay be in different locations than are shown in the figures. Conductancepatterns are next formed on one or both of the top and bottom conductivelayers in step 202. The conductance pattern(s) may include electricaltraces 106, contact pads 109 on a top surface of the substrate andcontact pads 108 on a bottom surface of the substrate as shown forexample in FIGS. 3 and 4. The traces 106 and contact pads 109, 108 (onlysome of which are numbered in the figures) are by way of example, andthe substrate 102 may include more traces and/or contact pads than isshown in the figures, and they may be in different locations than isshown in the figures. In one embodiment, the substrate 102 may includeone or more rows of contact pads 109 at opposed edges of the substrate102 as shown in FIG. 3. Further embodiments may employ a multi-layersubstrate, which include internal conductance patterns in addition tothose on the top and/or bottom surfaces.

In various embodiments, the finished semiconductor device may be used asa BGA (ball grid array) package. A lower surface of the substrate 102may include contact pads 108 for receiving solder balls as explainedbelow. In various embodiments, the finished semiconductor device 180 maybe an LGA (land grid array) package including contact fingers forremovably coupling the finished device 180 within a host device. In suchembodiments, the lower surface may include contact fingers instead ofthe contact pads that receive solder balls. The conductance pattern onthe top and/or bottom surfaces of the substrate 102 may be formed by avariety of suitable processes, including for example variousphotolithographic processes.

Referring again to FIG. 1, the substrate 102 may next be inspected instep 204. This step may include an automatic optical inspection (AOI).Once inspected, a solder mask 110 (FIG. 4) may be applied to thesubstrate in step 206. After the solder mask is applied, the contactpads, and any other areas to be soldered on the conductance patterns maybe plated, for example, with a Ni/Au, Alloy 42, or the like, in step 208in a known electroplating or thin film deposition process. The substrate102 may then undergo operational testing in step 210. In step 212, thesubstrate may be visually inspected, including for example an automatedvisual inspection (AVI) and a final visual inspection (FVI) to check forcontamination, scratches and discoloration. One or more of these stepsmay be omitted or performed in a different order.

Assuming the substrate 102 passes inspection, passive components 112(FIG. 3) may next be affixed to the substrate 102 in a step 214. The oneor more passive components may include for example one or morecapacitors, resistors and/or inductors, though other components arecontemplated. The passive components 112 shown are by way of exampleonly, and the number, type and position may vary in further embodiments.

Referring to FIG. 5, a number of semiconductor die 124 may next bestacked on the substrate 102 in step 220. The semiconductor die 124 mayfor example be memory die such a NAND flash memory die, but other typesof die 124 may be used. These other types of semiconductor die includebut are not limited to controller die such as an ASIC, or RAM such as anSDRAM. The semiconductor die 124 may further alternatively be used toform package 100 into a power semiconductor device such as for example aswitch or rectifier. Where multiple semiconductor die 124 are included,the semiconductor die 124 may be stacked atop each other in an offsetstepped configuration to form a die stack 120. There may be more thanone die stack 120, with alternating stacks stepped in oppositedirections. Embodiments may include different numbers of semiconductordie, including for example 1, 2, 4, 8, 16, 32 or 64 die. There may beother numbers of die in further embodiments. The die may be affixed tothe substrate and/or each other using a die attach film. As one example,the die attach film may be 8988UV epoxy from Henkel AG & Co. KGaA, curedto a B-stage to preliminarily affix the die 124 in the stack 120, andsubsequently cured to a final C-stage to permanently affix the die 124in the stack 120.

A redistribution layer (RDL) 126 may be affixed to the top of the diestack in step 222. The RDL 126 may be a rigid layer, formed for exampleof FR4and FR5, or a flexible layer, formed for example of polyimidetape. Referring to FIGS. 5-7, the RDL 126 may have bond pads 134 alongan edge of the RDL 126, similar in size and configuration to bond pads132 provided on the semiconductor die 124. (FIGS. 7 and 9 each show asingle semiconductor die 124 in the stack 120 for simplicity, but thesemiconductor package 100 shown in FIGS. 7 and 9 may include multiplesemiconductor die 124 as in the other illustrated embodiments). Bondpads 134 are shown along a single edge, but bond pads 134 may beprovided along two opposed or adjacent edges, along three edges or alongall four edges of the RDL 126.

The RDL 126 may further include a pattern of redistribution pads 130 onan upper surface. In embodiments, electrical traces may be providedbetween the RDL bond pads 134 and the redistribution pads 130 toeffectively redistribute the bond pads 134 over the upper surface of theRDL 126. There may be more bond pads 134 than are shown, so that eachbond pad 134 may be connected to redistribution pad 130. A passivationlayer 136 may be applied over the electrical traces and redistributionpads 130, which passivation layer 136 is then etched or otherwisedeveloped to expose the redistribution pads 130. In step 224, solderballs 140 may be applied to the redistribution pads 130 as shown inFIGS. 6 and 7. The pattern of redistribution pads 130 and solder balls140 shown in the figures is by way of example, and may vary in furtherembodiments. Other electrical connectors may be provided instead ofsolder balls 140, including but not limited to solder paste.

Referring now to views of FIGS. 8 and 9, the respective die 124 in thestack 120 may next be electrically connected to each other the substrate102 and RDL 126 in step 230 using wire bonds 138. As shown, eachsemiconductor die 124 may include a row of die bond pads 132 along anedge of the die 124. It is understood that each die 124 may include manymore die bond pads 132 than is shown in FIG. 9. Each die bond pad 132 inthe row of a semiconductor die may be electrically connected to thecorresponding die bond pad 132 in the row of the next adjacentsemiconductor die using a wire bond 138. Each die bond pad 132 of thebottom semiconductor die 124 may be electrically connected to thecorresponding contact pad 109 in a row of contact pads on substrate 102using a wire bond 138.

Although wire bonds 138 may be formed by a variety of technologies, inone embodiment, the wire bonds 138 may be formed as ball bonds, thoughother types of bonds are contemplated. The wire bonds 138 are showngenerally in a straight vertical column from one layer to the next inthe die stack 120, and to the substrate 102 and RDL 126. However, one ormore of the wire bonds may extend diagonally from one layer to the nextin alternative embodiments. Further, it may be that a wire bond skipsone or more layers in the die stack 120. It is conceivable that the wirebond step 230 be performed before the solder ball bonding step 224 infurther embodiments.

Following electrical connection of the die stack 120 and the formationof solder balls on RDL 126, the semiconductor package 100 may beencapsulated in a mold compound 142 in a step 234 and as shown in FIGS.10 and 11. The semiconductor device may be placed within a mold chase144 comprising upper mold plate 146 and lower mold plate 148. Moltenmold compound 142 may then be injected into the mold chase 144 to encasethe components of the semiconductor package 100 in a protectiveenclosure in for example a compression molding process. Mold compound142 may include for example solid epoxy resin, Phenol resin, fusedsilica, crystalline silica, carbon black and/or metal hydroxide. Suchmold compounds are available for example from Sumitomo Corp. andNitto-Denko Corp., both having headquarters in Japan. Other moldcompounds from other manufacturers are contemplated. The mold compoundmay be applied according to other known processes, including by transfermolding or injection molding techniques.

It is a feature of the present technology that portions of the solderballs 140 of the RDL 126 (also referred to herein as “RDL solder balls140”) remain exposed at an exterior surface of the mold compound 142.Therefore, the lower mold plate 148 may be lined with a release film150. The tips of the RDL solder balls 140 embed within the release film150 when the semiconductor package 100 is placed within the mold chase144. The release film may be for example a polymer which is flexible andto a degree soft, so that, when the package 100 is inserted into themold chase 144, the tips of the RDL solder balls 140 embed within therelease film 150. The release film maintains its structure throughoutthe encapsulation process, so that the mold compound 142 encases the RDL126, die 124 and wire bonds 138, but the tips of the RDL solder balls140 remain exposed through a surface of the mold compound 142, at thecompletion of the encapsulation process. Upon completion, the releasefilm 150 may be easily removed from the RDL solder balls. One example ofa suitable release film 150 is a fluoropolymer, such as for exampleFluon® ETFE film, marketed by AGC Chemicals Americas, Inc, havingoffices in Pennsylvania, USA. Other polymers are possible for releasefilm 150.

In step 236, solder balls 154 (FIG. 11) may be affixed to the contactpads 108 on a lower surface of substrate 102 of the package 100. Thesolder balls 154 (also referred to herein as “substrate solder balls154”) may be used to affix the semiconductor package 100 to a hostdevice (not shown) such as a printed circuit board. As explained below,the solder balls 154 may alternatively be used to affix thesemiconductor package 100 to one or more other semiconductor packages.

As noted above, the semiconductor package 100 may be formed on a panelof substrates. After formation and encapsulation of the packages 100,the packages 100 may be singulated from each other in step 240 to form afinished semiconductor package 100 as shown in FIG. 11. Thesemiconductor packages 100 may be singulated by any of a variety ofcutting methods including sawing, water jet cutting, laser cutting,water guided laser cutting, dry media cutting, and diamond coating wirecutting. While straight line cuts will define generally rectangular orsquare shaped semiconductor packages 100, it is understood thatsemiconductor package 100 may have shapes other than rectangular andsquare in further embodiments of the present technology.

Before, during or after the formation of encapsulated semiconductorpackage 100, a group of one or more second semiconductor packages 170may be formed in step 242 and as shown for example in FIGS. 12-18. Inembodiments, the group of one or more packages 170 may be flash memorypackages formed by the same steps as the package 100, such as forexample the above-described steps 200-240 of FIG. 3. However, it is afurther feature of the present technology that semiconductor package(s)170 need not be the same configuration or same type of semiconductorpackage as package 100. As examples, the group of one or more packages170 may comprise other types of memory packages, such as SDRAM and othertypes of RAM. The group of one or more packages 170 may alternatively oradditionally comprise controller die, such as an ASIC, or a powersemiconductor device such as a switch or rectifier. Other types ofsemiconductor packages are contemplated as being included within thegroup of one or more packages 170.

In step 244, the group of one or more second semiconductor packages 170may be mounted to the first semiconductor package 100. As thesemiconductor package 170 has electrical connections on both of itsmajor surfaces (RDL solder balls 140 on the top surface and substratesolder balls 154 on the bottom surface), it is a further feature of thepresent technology that the group of one or more second semiconductorpackages 170 may be affixed above and/or below the package 100. In thefollowing description and as used herein, semiconductor packagesincluding RDL solder balls 140 extending through a surface of the moldcompound are referred to as the semiconductor package 100. Packageswhich do not include RDL solder balls 140 are referred to as one of thesemiconductor packages 170.

FIG. 12 shows a second group of three semiconductor packages 170physically and electrically connected the semiconductor package 100 bythe RDL solder balls 140 to form a semiconductor device 180. Inparticular, the semiconductor packages 170 may have contact pads on abottom surface in a pattern that matches the pattern of RDL solder balls140 with which the contact pads mate and connect, as in a solder reflowstep. The semiconductor device 180 is physically and electricallyconnected to a host device 174, such as for example a printed circuitboard (PCB), by the substrate solder balls 154 on the package 100. Thus,signals and voltages are exchanged between the group of semiconductorpackages 170 and the host device 174 through the semiconductor package100.

In embodiments, once affixed to each other, both packages 100 and 170 ofdevice 180 may be encapsulated together in a further encapsulationprocess. Alternatively, any space between the packages 100 and 170 maybe back-filled with an epoxy resin 176. In further embodiments, nofurther encapsulation or back-fill steps are performed, and the packages100 and 170 are held together simply by the solder balls 140.

In one example, the semiconductor package 100 in FIG. 12 may include aplurality of non-volatile memory die, such as for example NAND flashmemory die. As indicated above, the package 100 may alternativelyinclude one or more semiconductor die and may alternatively be avolatile memory package, a controller, a power semiconductor package orsome other type of semiconductor package. In one example, the individualsemiconductor packages 170 may include one or more semiconductor die,and may be configured as non-volatile memory packages, volatile memorypackages, controllers and/or power semiconductor packages. Other typesof semiconductor devices are contemplated for packages 170. The packages170 may each be of the same type, or may be different types. Forexample, one of the packages may be a controller, one may be volatilememory and one may be a power semiconductor package. Other combinationsare contemplated for packages 170.

In the example shown in FIG. 12, each of the three semiconductorpackages 170 are shown mounted to three rows of RDL solder balls 140 ona surface of the semiconductor package 100. This is by way of exampleonly, and the semiconductor packages 170 may be mounted to the package100 using other numbers of rows of RDL solder balls 140. It is furthercontemplated that the packages 170 may be different sizes and/or usedifferent numbers of rows of RDL solder balls 140 to affix to package100. While three packages 170 are shown in the example of FIG. 12, theremay be greater or fewer numbers of packages 170 affixed to RDL solderballs 140 of package 100, including for example 1, 2, 4, 5 or 6 packages170. While all rows of RDL solder balls 140 are shown mounted to apackage 170, some of the RDL solder balls 140 may be left without anattachment to a package 170.

As noted above, semiconductor packages 100 may be singulated intoindividual semiconductor packages, each including a single group ofvertically stacked semiconductor die mounted on the substrate 102.However, as shown for example in FIGS. 13 and 14, a single semiconductorpackage 100 may alternatively be singulated to include multiple groupsof vertically stacked semiconductor die on the substrate 102. Thesemiconductor package 100 of FIGS. 13 and 14 may be fabricated asdescribed above, but singulated to include multiple semiconductor diestacks instead of a single semiconductor die stack.

In the embodiment of FIG. 13, a single semiconductor package 170 may bemounted to the RDL solder balls 140 on the separate RDLs 126 ofsemiconductor package 100 to form a finished semiconductor device 180.In the embodiment of FIG. 14, multiple semiconductor packages 170 may bemounted to the RDL solder balls 140 of the multiple RDLs 126 ofsemiconductor package 100 to form a finished semiconductor device 180.Each of the packages 100 and 170 in FIGS. 13 and 14 may include a singlesemiconductor die or multiple semiconductor die (one or more of thepackages 100, 170 may have different numbers of semiconductor die). Eachof the packages 100 and 170 in FIGS. 13 and 14 may function as avolatile memory, a non-volatile memory, a controller, a power device orhave some other functionality (one or more of the packages 100, 170 mayhave different functionalities).

The embodiments of FIGS. 13 and 14 show three stacks of semiconductordie in the semiconductor package 100, but there may be greater or fewerthan three stacks in further embodiments. The embodiment of FIG. 14shows three semiconductor packages 170 mounted to semiconductor package100, but there may be greater or fewer than three semiconductor packages170 in further embodiments, including for example 1, 2, 4, 5 or 6packages. In the embodiment of FIG. 14, the semiconductor device 180 mayfunction as a single integrated semiconductor device, or it may functionas three separate and independent semiconductor devices.

In the embodiments of FIGS. 13 and 14, once affixed to each other, thepackages 100 and 170 of device 180 may be encapsulated together in afurther encapsulation process. Alternatively, any space between thepackages 100 and 170 may be back-filled with an epoxy resin 176. Infurther embodiments, no further encapsulation or back-fill steps areperformed, and the packages 100 and 170 are held together simply by thesolder balls 140. The semiconductor devices 180 of FIGS. 13 and 14 maybe mounted to a host device (not shown) such as a PCB by substratesolder balls 154 of package 100.

FIG. 15 shows a further embodiment where a single semiconductor package170 is mounted to the RDL solder balls 140 of three separate andindependent semiconductor packages 100. FIG. 15 may include the samecomponents and features of the embodiment shown in FIG. 13, with theexception that the individual semiconductor die stacks and FIG. 15 aresingulated to be separate semiconductor packages.

The embodiments described above with respect to FIGS. 12-14 comprisesemiconductor devices 180 including two stacked and verticallyintegrated levels of semiconductor packages. Further embodiments of thepresent technology may comprise semiconductor devices including morethan two stacked and vertically integrated levels of semiconductorpackages. For example, FIGS. 16 and 17 each show three verticallyintegrated levels of semiconductor packages. A bottom level may compriseone or more semiconductor packages 100 mounted to a host device (notshown) by substrate solder balls 154. A second level may comprise one ormore semiconductor packages 100 mounted to the RDL solder balls 140 ofthe bottom level semiconductor package(s) 100. Note that in such aconfiguration, the substrate solder balls 154 may be omitted from thesecond level semiconductor package(s) 100, so that the RDL solder balls140 of the bottom level are soldered to contact pads 108 on thesubstrate(s) 102 of the second level semiconductor package(s) 100. Athird level may comprise one or more semiconductor packages 170 mountedto the RDL solder balls 140 of the second level semiconductor package(s)100.

While FIGS. 16 and 17 show specific examples of semiconductor devices180 including three levels of semiconductor packages, it is understoodthat semiconductor devices 180 of FIGS. 16 and 17 we have a variety ofother configurations. Each level may include one or more semiconductorpackages, and each semiconductor package may include one or moresemiconductor die. Where a semiconductor package on a given levelincludes multiple semiconductor die, though semiconductor die may beprovided in a single vertical stack or multiple side-by-side verticalstacks. Each of the packages 100 and 170 in FIGS. 16 and 17 may functionas a volatile memory, a non-volatile memory, a controller, a powerdevice or have some other functionality (one or more of the packages100, 170 may have different functionalities).

In the embodiments of FIGS. 16 and 17, once affixed to each other, thepackages 100 and 170 of device 180 may be encapsulated together in afurther encapsulation process. Alternatively, any space between thepackages 100 and 170 may be back-filled with an epoxy resin 176, twoseparate layers in this embodiment. In further embodiments, no furtherencapsulation or back-fill steps are performed, and the packages 100 and170 are held together simply by the solder balls 140 in the two packages100. The semiconductor devices 180 of FIGS. 16 and 17 may be mounted toa host device (not shown) such as a PCB by substrate solder balls 154 ofthe bottom package 100. While three levels of vertically integratedsemiconductor packages 100, 170 are shown in FIGS. 16 and 17, there maybe more than three levels of vertically integrated semiconductorpackages 100, 170 in further embodiments.

The pattern of RDL solder balls 140 in semiconductor package 100,including number, arrangement and spacing, may be provided incoordination with the number of second level packages 170 and thepattern of substrate contact pads 108 in those second level packages170. For example, FIG. 18 shows a top surface of a semiconductor package100 including a pattern of RDL solder balls 140. The RDL solder balls140 in this example are arranged in six groups, to receive six distinctsecond level semiconductor packages 170 (one of which is shown in bottomview). As shown, each group has a pattern of RDL solder balls 140 thatis coordinated with the pattern of substrate contact pads 108 of thepackages 170 to be mounted on the package 100. In particular, thenumber, arrangement and spacing of the RDL solder balls 140 may beconfigured to match the number, arrangement and spacing of the substratecontact pads 108. The substrate contact pads 108 in the other packages170 (not shown) in the example of FIG. 18 may have the same pattern ofas the group of substrate contact pads 108 shown.

During and after completion of the respective packages 100 and 170 (butbefore being affixed to each other), each of the packages 100 and 170may be tested for operation and quality. It is a feature of the presenttechnology to provide a higher yield of semiconductor devices. Forexample, where a variety of semiconductor die such as non-volatilememory, volatile memory and a controller are packaged together, a defectmay require discarding the entire package. However, by assembling andtesting individual components into packages, and then integrating thosepackages together, the likelihood of having to discard an entiresemiconductor device is minimized.

Additionally, defects in fabricated semiconductor packages are often notfatal, but result in finished semiconductor packages of varying quality.Finished semiconductor packages may be tested in a “binning” process,and categorized based on their performance. It is a further feature ofthe present technology that binning allows semiconductor packages oflike quality to be affixed to each other. This allows for higher overallquality of the produced semiconductor devices 180 as compared to devicesincluding a single package having the same number of semiconductor die.

In summary, in one example, the present technology relates to asemiconductor device, comprising: a first semiconductor package,comprising: a first substrate, a first group of one or moresemiconductor die, a redistribution layer having a plurality of solderballs affixed to a surface of the redistribution layer, and a first moldcompound encapsulating at least a portion of the first semiconductorpackage, at least a portion of the solder balls extending through asurface of the first mold compound; and a group of one or more secondsemiconductor packages, comprising: at least one second substratecomprising contact pads on at least one surface of the at least onesecond substrate, a second group of one or more semiconductor die, andat least one second mold compound encapsulating at least a portion ofthe at least one second semiconductor package; a pattern of the solderballs extending through the surface of the first mold compound matchinga pattern of the contact pads on the at least one surface of the atleast one second substrate, the solder balls being affixed to thecontact pads to couple the first semiconductor package to the group ofone or more second semiconductor packages.

In another example, the present technology relates to a semiconductordevice, comprising: a first group of one or more first semiconductorpackages, comprising: at least a first substrate, a first group of oneor more first semiconductor die, a redistribution layer having aplurality of solder balls affixed to a surface of the redistributionlayer, and a first mold compound encapsulating at least a portion of thefirst group of one or more first semiconductor packages, the solderballs being exposed through a surface of the first mold compound; and asecond group of one or more second semiconductor packages, comprising:at least one second substrate comprising contact pads on at least onesurface of the at least one second substrate, a second group of one ormore second semiconductor die, and at least one second mold compoundencapsulating at least a portion of the second group of one or moresecond semiconductor packages; a pattern of the solder balls ofredistribution layer matching a pattern of the contact pads on the atleast second substrate, the solder balls being affixed to the contactpads to couple the first group of one or more first semiconductorpackages to the second group of one or more second semiconductorpackages.

In a further example, the present technology relates to a semiconductordevice, comprising: a first group of one or more first semiconductorpackages, comprising: at least a first substrate means for transferringsignals to and from semiconductor die, a first group of one or morefirst semiconductor die mounted on the substrate means, redistributionmeans for electrically connecting a plurality of contact pads on theredistribution means to a plurality of soldering means affixed to asurface of the redistribution means, and first encapsulation means forencapsulating at least a portion of the first group of one or more firstsemiconductor packages, the soldering means being exposed through asurface of the first encapsulation means; and a second group of one ormore second semiconductor packages, comprising: at least one secondsubstrate means for transferring signals to and from semiconductor die,the at least one second substrate means comprising electrical connectormeans on at least one surface of the at least one second substrate, asecond group of one or more second semiconductor die, and secondencapsulation means encapsulating at least a portion of the second groupof one or more second semiconductor packages; a pattern of the solderingmeans of the redistribution means matching a pattern of the electricalconnector means on the at least second substrate, the soldering meansbeing affixed to the electrical connector means to couple the firstgroup of one or more first semiconductor packages to the second group ofone or more second semiconductor packages.

In another example, the present technology relates to a semiconductordevice, comprising: at least one first semiconductor package, including:a first substrate including a first plurality of interconnect features,wherein the first plurality of interconnect features creates a firstpattern; at least one first group of semiconductor die electricallyconnected to the first plurality of interconnect features; a first layerconnected to the first group of semiconductor dies, the first layerhaving a second plurality of interconnect features affixed to a surfaceof the first layer, wherein the second plurality of interconnectfeatures are electrically connected to the first group of semiconductordie, further wherein the second plurality of interconnect featurescreates a second pattern; and an encapsulation layer positioned aroundthe first semiconductor package, wherein the first plurality ofinterconnect features are exposed through a surface of the firstencapsulation layer; at least one second semiconductor package,including: a second substrate comprising a plurality of contact pads ona first surface of the second substrate, wherein the plurality ofcontact pads creates a third pattern; at least one second groupsemiconductor die; and a second encapsulation later positioned aroundthe at least one second semiconductor package; wherein, at least one ofthe pattern of the first and second plurality of interconnect featuresmatches the third pattern of the plurality of contact pads such that thefirst or second plurality of interconnect feature are able to beelectrically connected to the plurality of contact pads.

The foregoing detailed description of the technology has been presentedfor purposes of illustration and description. It is not intended to beexhaustive or to limit the technology to the precise form disclosed.Many modifications and variations are possible in light of the aboveteaching. The described embodiments were chosen in order to best explainthe principles of the technology and its practical application tothereby enable others skilled in the art to best utilize the technologyin various embodiments and with various modifications as are suited tothe particular use contemplated. It is intended that the scope of thetechnology be defined by the claims appended hereto.

We claim:
 1. A semiconductor device, comprising: a first semiconductorpackage, comprising: a first substrate, a first group of one or moresemiconductor die, a redistribution layer having a plurality of solderballs affixed to a surface of the redistribution layer, and a first moldcompound encapsulating at least a portion of the first semiconductorpackage, at least a portion of the solder balls extending through asurface of the first mold compound; and a group of one or more secondsemiconductor packages, comprising: at least one second substratecomprising contact pads on at least one surface of the at least onesecond substrate, a second group of one or more semiconductor die, atleast one second mold compound encapsulating at least a portion of theat least one second semiconductor package; and a pattern of the solderballs extending through the surface of the first mold compound matchinga pattern of the contact pads on the at least one surface of the atleast one second substrate, the solder balls being affixed to thecontact pads to couple the first semiconductor package to the group ofone or more second semiconductor packages; wherein the solder ballsextend through the surface of the first mold compound by the solderballs embedding in a release film in a mold chase used to form the firstmold compound, and removing the release film after the first moldcompound is formed.
 2. The semiconductor device of claim 1, whereinsignals communicated between the group of one or more secondsemiconductor packages and a host device occur through the firstsemiconductor package.
 3. The semiconductor device of claim 1, wherein afunctionality of the first package is different than a functionality ofthe group of one or more second semiconductor packages.
 4. Thesemiconductor device of claim 1, wherein the group of one or more secondsemiconductor packages comprise a plurality of semiconductor packagesmounted to a surface of the first semiconductor package.
 5. Thesemiconductor device of claim 4, wherein two or more packages of theplurality of second semiconductor packages have the same functionality.6. The semiconductor device of claim 4, wherein two or more packages ofthe plurality of second semiconductor packages have differentfunctionalities than each other.
 7. The semiconductor device of claim 1,wherein the group of one or more semiconductor die in the firstsemiconductor package comprises a plurality of semiconductor die stackedin a single stack on the first substrate.
 8. The semiconductor device ofclaim 1, wherein the group of one or more semiconductor die in the firstsemiconductor package comprises a plurality of semiconductor die stackedin plurality of stacks on the first substrate.
 9. A semiconductordevice, comprising: a first group of one or more first semiconductorpackages, comprising: at least a first substrate, a first group of twoor more first semiconductor die, a redistribution layer having aplurality of solder balls affixed to a surface of the redistributionlayer on each of the two or more first semiconductor die of the firstgroup of two or more semiconductor die, and a first mold compoundencapsulating at least a portion of the first group of one or more firstsemiconductor packages, the solder balls being exposed through a surfaceof the first mold compound; and a second semiconductor package,comprising: a second substrate comprising contact pads on at least onesurface of the second substrate, a second group of one or more secondsemiconductor die, a second mold compound encapsulating at least aportion of the second semiconductor package; and a pattern of the solderballs of redistribution layers on the two or more first semiconductordies together matching a pattern of the contact pads on the secondsubstrate, the solder balls being affixed to the contact pads to couplethe first group of one or more first semiconductor packages to thesecond semiconductor package.
 10. The semiconductor device of claim 9,wherein the first group of one or more first semiconductor packagescomprise a plurality of first semiconductor packages.
 11. Thesemiconductor device of claim 10, wherein two or more packages of theplurality of first semiconductor packages have the same functionality.12. The semiconductor device of claim 10, wherein two or more packagesof the plurality of first semiconductor packages have differentfunctionality than each other.
 13. The semiconductor device of claim 9,wherein the first group of one or more first semiconductor packagescomprise a single semiconductor package.
 14. A semiconductor device,comprising: a first semiconductor package, comprising: a firstsubstrate, a first group of one or more semiconductor die, aredistribution layer having a plurality of solder balls affixed to asurface of the redistribution layer, and a first mold compoundencapsulating at least a portion of the first semiconductor package, atleast a portion of the solder balls extending through a surface of thefirst mold compound; and a group of two or more second semiconductorpackages mounted on a surface of the first semiconductor package, eachof the two or more second semiconductor packages comprising: a secondsubstrate comprising contact pads on a surface of the second substrate,a second group of one or more semiconductor die, a second mold compoundencapsulating each of the two or more second semiconductor packages; anda pattern of the solder balls extending through the surface of the firstmold compound matching a pattern of the contact pads on the surfaces ofeach of the second substrates together, the solder balls being affixedto the contact pads to couple the first semiconductor package to thegroup of two or more second semiconductor packages.
 15. Thesemiconductor device of claim 14, wherein a functionality of the firstpackage is different than a functionality of at least one of the groupof two or more second semiconductor packages.
 16. The semiconductordevice of claim 14, wherein two or more packages of the group of two ormore second semiconductor packages have the same functionality.
 17. Thesemiconductor device of claim 14, wherein two or more packages of thegroup of two or more second semiconductor packages have differentfunctionalities than each other.